Booster: An Acceleration-Based Verification Framework for Array Programs

Towards Beneficial Hardware Acceleration in HAVEN: Evaluation of Testbed Architectures

Functional verification is a widespread technique to check whether a hardware system satisfies a given correctness specification. As the complexity of modern hardware systems rises rapidly, it is a challenging task to find appropriate techniques for acceleration of this process. In our previous work, we developed HAVEN, an open verification framework that enables hardware acceleration of functi...

A New Acceleration-Based Combination Framework for Array Properties

This paper presents an acceleration-based combination framework for checking the satisfiability of classes of quantified formulæ of the theory of arrays. We identify sufficient conditions for which an ‘acceleratability’ result can be used as a black-box module inside such satisfiability procedures. Besides establishing new decidability results and relating them to results from recent literature...

FPGA implementation of an embedded face detection system based on LEON3

This paper presents an FPGA face detection embedded system. In order achieve acceleration in the face detection process a hardware-software codesign technique is proposed. The paper describes the face detection acceleration mechanism. It also describes the implementation of an IP module that allows hardware acceleration.

Hardware-Accelerated Formal Verification

A semi-formal verification technique, which performs a brute-force compiled simulation with a sophisticated search space pruning, has been proposed and shown to be competitive with the state-of-the-art SAT-based verification techniques [3]. This paper presents a novel approach for accelerating the semi-formal verification by utilizing hardware/software co-execution. To maximize the gain from ha...

Runtime verification of programs using rule-based active system